1. Field of the Invention
The present invention relates to an apparatus and method for processing data. More particularly, the present invention relates to an apparatus and method for processing data among processors sharing a storage unit.
2. Description of the Related Art
A communication device according to the related art performs various functions. A function may be characterized as performing at least one of two functions—a function performing a User Interface (UI) and executing an application, and a communication function. For convenience, the function performing the UI and executing the application is referred to as a ‘non-communication function’.
According to the related art, a communication device may process the non-communication function and the communication function using one processor. However, as a need for a faster communication speed increases and as complexity of applications increases, a communication device may perform the non-communication function and the communication function using a plurality of processors. For example, when a communication device according to the related art is a smart phone, the communication device performs a non-communication function using an Application Processor (AP) and performs a communication function using a Communication Processor (CP). The AP and the CP may be implemented as separate chips, or one chip.
According to the related art, data may be communicated (e.g., via transmission/reception) between the AP and the CP in order to transmit/receive data and process data using a communication network. For example, if a Long-Term Evolution (LTE) terminal performs a File Transfer Protocol (FTP) download operation, data received through a CP is transferred to an AP, and thereafter the AP performs a data processing operation such as data storage. In contrast, if the LTE terminal performs an upload operation, the AP transfers data to be uploaded to the CP, and thereafter the CP transmits the data to be uploaded through a communication network. In a video streaming context such as the streaming of video from an internet service such as, for example, YouTube®, the CP transfers received data to the AP, the AP processes the data transferred from the CP and displays the processed data on a screen.
As described above, in a communication device according to the related art, data transmission/reception between an AP and a CP frequently occurs. As such, the communication device according to the related art uses a serial interface such as a Universal Serial Bus (USB), a High Speed Integrated Circuit (HSIC), and a Secure Digital Input Output (SDIO), a shared memory such as a Dual Port Random Access Memory (DPRAM) and the like. Specially, if the AP and the CP are implemented as one chip, the AP and CP share a bus, and consequently, a communication device according to the related art uses a scheme for transmitting/receiving data using a shared memory included in the chip.
FIG. 1 schematically illustrates a process in which each of an AP and a CP uses a DRAM and processes data through an external InterFace (IF) unit in a communication device according to the related art.
Referring to FIG. 1, the communication device includes an AP 110, a Dynamic Random Access Memory (DRAM) 120 (e.g., such as a Low Power Double Data Rate (LPDDR2)), a CP 130, and a DRAM 140 (e.g., such as an LPDDR2). The AP 110 includes a Central Processing Unit (CPU) 111 and an IF unit 113, and the CP 130 includes a CPU 131, an IF unit 133, and a MOdulator/DE-Modulator (MODEM) 135.
The MODEM 135 writes data corresponding to decoded data stored in a decoder buffer to the LPDDR2 140 in step 151. The CPU 131 reads/writes data necessary for performing a communication function from/to the DRAM 140 in step 152. The CPU 131 configures Internet Protocol (IP) packet data using a communication standard protocol such as, for example, an L1/L2/L3, a Network Application Support (NAS), and the like. In step 153 and 154, the data stored in the DRAM 140 (e.g., the IP packet data) is transferred between the IF units 133 and 113 to the AP 110. In the AP, the IP packet data is written to the DRAM 120 in step 155.
When writing the data stored in the DRAM 140 to the DRAM 120 through the IF units 133 and 113, a process for transmitting/receiving a control message among the CPU 131, the IF units 133 and 113, and the CPU 111 is necessary in steps 157, 158, and 159.
The CPU 111 reads/writes data necessary for performing an application function from/to the DRAM 120 in step 156.
According to the related art, each of the IF units 133 and 113 may include a Direct Memory Access (DMA) unit. Conversely, each of the IF units 133 and 113 may use an external general DMA. A CPU or a separate processor may read/write data. The data processing process as described in FIG. 1 is for a DownLink (DL) communication. However, one ordinary skill in the art would understand that the data processing process may be performed in reverse for an UpLink (UL) communication.
FIG. 2 schematically illustrates a process in which an AP and a CP share a DRAM using a Chip to Chip (C2C) scheme and process data in a communication device according to the related art.
Referring to FIG. 2, the communication device includes an AP 210, a CP 220, and a DRAM 230 (e.g., an LPDDR2). The AP 210 includes a CPU 211, an IF unit 213, and a C2C IF unit 215, and the CP 220 includes an IF unit 221, a CPU 223, a MODEM 225, and a C2C IF unit 227. The DRAM 230 includes a CP region 231 in which data related to the CP 220 is stored, and an AP region 233 in which data related to the AP 210 is stored.
The MODEM 225 writes data corresponding to decoded data stored in a decoder buffer to the CP region 231 in step 241. The CPU 223 reads/writes data necessary for performing a communication function from/to the CP region 231 in step 242. The CPU 223 configures IP packet data using a communication standard protocol such as an L1/L2/L3, a NAS, and the like. The data stored in the CP region 231 (e.g., the IP packet data) is written to the AP region 233 through the external IF units 221 and 213 in steps 243, 244, and 245.
When writing the data stored in the CP region 231 to the AP region 223 through the IF units 221 and 213, a process for transmitting/receiving a control message among the CPU 223, the IF units 221 and 213, and the CPU 211 is necessary in step 247, and 248.
The CPU 211 reads/writes data necessary for performing an application function from/to the AP region 223 in step 246.
According to the related art, each of the IF units 221 and 213 may include a DMA unit. Conversely, each of the IF units 221 and 213 may use an external general DMA, or a separate processor may read/write data. The data transmitting/receiving process as described in FIG. 2 is for a DL communication. However, one of ordinary skill in the art would understand that the data processing process may be performed in reverse for a UL communication.
In the communication device as described in FIGS. 1 and 2, the data transmitting/receiving process may result in a limitation for a possible data throughput based on a Band Width (BW) for a C2C scheme because the number of DRAM read/write operations is large in the data transmitting/receiving process. For example, in an LTE Category-3 DL, even though a CP uses a scheme optimized with a zero copy scheme, the CP may write decoded data to a DRAM, read the data written to the DRAM from the DRAM for deciphering, write the deciphered data to the DRAM, and perform a read operation for transferring user data processed with a protocol to an AP. The CP may read/write 100 Mbps data from/to the DRAM at least four times.
If a CP does not use a zero copy scheme, a data copy operation is necessary in order to generate segmented data as an IP packet. Consequently, the number of data read/write operations on a DRAM increases (e.g., a data read/write operation for a data ciphering/deciphering is not shown in FIGS. 1 and 2).
If DL/UL data is simultaneously transmitted/received, a total of four data read/write operations is necessary in a UL as well as a DL. Accordingly, a total of eight data read/write operations is necessary for the DL and the UL.
If a data throughput increases, a congestion situation occurs on a Dynamic Memory Controller (DMC) for a DRAM access in the data processing process in FIG. 1. Such congestion on the DMC may result in a bottleneck situation on an access to a DRAM and a decrease of a processing speed for an external IF.
If a data throughput increases, a congestion situation occurs on a C2C in the data processing process in FIG. 2. Such congestion on the C2C may result in a limitation for a high-speed data processing and a decrease of a processing speed for an external IF.
According to the related art, a data transmission speed between an AP and a CP may be faster than a maximum data transmission speed of the CP. For example, in a DL, when a packet error occurs, data transmission may not be possible until a related packet is received, and relatively more data is transferred to an AP all at once according to a retransmission completion for the related packet. In a UL, more data than data corresponding to a maximum speed which a CP supports may be transferred from an AP to a CP according to an operation of an application which the AP processes. In such cases, a CP may not operate normally due to a momentary increase for a data transmission speed through an IF.
Therefore, a need exists for an apparatus and method for processing data between processors sharing a storage unit.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present invention.